Technical Field
The present disclosure relates to non-volatile memories and in particular to a memory array and memory cell structure of the type described in the US application 2013/0228846, which is hereby incorporated by reference in its entirety.
Description of the Related Art
As a reminder, FIG. 1 represents such a memory array structure MA0 and shows memory cells Mi,j, M1−1,j, Mi,j−1, Mi−1,j+1 of the above-mentioned type, belonging here to two adjacent physical pages Pi, Pi−1 of the memory array, of respective ranks “i” and “i−1”. The memory cells Mi,j, Mi−1,j, Mi,j+1, Mi−1,j+1 are read- and write-accessible through bit lines BLj, BLj+1, a word line WLi−1,i and control gate lines CGLi, CGLi−1. Each memory cell comprises a floating-gate transistor, respectively Ti,j, Ti−1,j, Ti,j+1, Ti−1,j+1. The drain terminals D of the transistors Ti,j, Ti−1,j are connected to the bit line BLj and the drain terminals of the transistors Ti,j+1, Ti−1,j+1 are connected to the bit line BLj+1. The control gates CG of the transistors Ti,j, Ti,j+1 are connected to the control gate line CGLi and the control gates CG of the floating-gate transistors Ti−1,j, Ti−1,j+1 are connected to the control gate line CGLi−1.
Furthermore, each floating-gate transistor Ti,j, Ti−1,j, Ti,j+1, Ti−1,j+1 has its source terminal coupled to a source line SL through a select transistor ST. The select transistors ST of the memory cells Mi,j and Mi−1,j share the same control gate CSG and the two memory cells are thus referred to as “twins”. Similarly, memory cells Mi,j+1 and Mi−1,j+1 are twin memory cells and their select transistors ST have a common control gate CSG. Each common control gate is preferentially a vertical gate embedded in a substrate receiving the memory array MA0, the source line SL also being an embedded line. These common control gates CSG, or twin memory cell select gates, are connected to the word line WLi−1,i.
Such memory cells are channel-erased or programmed, i.e., by putting the substrate to a positive erase voltage or negative programming voltage causing electric charges to be extracted from their floating gates or electric charges to be injected into their floating gates, by Fowler Nordheim effect.
More particularly, a memory cell is erased by combining the positive voltage applied to the substrate with a negative voltage applied to the control gate of its floating-gate transistor, while the control gate of the floating-gate transistor of the twin memory cell receives a positive erase-inhibit voltage preventing it from being simultaneously erased (FIG. 11 of the above-mentioned application).
Similarly, a memory cell is programmed by combining a negative voltage applied to the bit line of the memory cell and to the substrate, with a positive voltage applied to the control gate of its floating-gate transistor, while the control gate of the floating-gate transistor of the twin memory cell receives a negative program-inhibit voltage preventing it from being simultaneously programmed (FIG. 12 of the above-mentioned application).
Finally, a memory cell is read by applying a positive voltage to the control gate of its floating-gate transistor, as well as a positive voltage to the corresponding bit line, while the twin memory cell, which is connected to the same bit line, receives on its control gate a negative read-inhibit voltage preventing it from being simultaneously read (FIG. 9 of the above-mentioned application).
This memory array structure having twin memory cells comprising a shared vertical select gate embedded in the substrate, offers the advantage of having a small footprint. The channel erase method used with this memory array structure is well suited to the production of a page-erasable memory array but less so to the production of a word-erasable memory array. This emerges by comparing the word-erasable memory array represented in FIG. 24 of the above-mentioned application, with the page-erasable memory array represented in FIG. 23 of this application, the former being more complex than the latter. Therefore, for the memory array to be word-erasable, each control gate line CGL, instead of being connected to all the memory cells of a page, must be divided into a plurality of control gate lines with one control gate line per word. This causes a noticeable complexification of the word line and column decoders, and requires providing various voltage switches to control, within each page, the control gate lines of the different words.
It can thus be desired to provide an improvement of this memory array and memory cell structure that is more appropriate for the implementation of a word-erasable memory, and does not complexify the control units of the memory array.
This conventional memory array and memory cell structure also employ a word line decoder capable of applying a positive read voltage to a memory cell that must be read, while applying a negative read-inhibit voltage to its twin memory cell, as explained above.
It can thus also be desired to provide another improvement of this memory array and memory cell structure that enables a memory cell to be read without applying any negative voltage to the twin memory cell.